The present invention relates to a cache address comparator and, more particularly, to a cache address comparator having an internal SRAM memory that is capable of being addressed in either the normal or the burst mode.
Cache address comparators, such as model number TMS-2150 by Texas Instruments of Dallas Tex., have been known in the art for a number of years. The TMS-2150, when in a memory access mode, compares the contents of the memory location addressed by signals A0-A8 with the data signals D0-D7, including generated parity. A true comparison sets the MATCH output HIGH. This indicates to an attached processor that the addressed data is available in an associated cache memory. A true comparison is often called a `hit` or a match, and a not-true comparison is called a `miss`.
A `hit` typically indicates to the attached processor that it may immediately access the data from the associated cache memory. A `miss`, on the other hand, indicates to the attached processor that it must start an interrupt sequence to access the desired data from the main memory. For lower speed, simple memory hierarchies the simple indication of a `hit` or a `miss` is acceptable, but for a high speed, multi-level cache memory hierarchy in a multi-stage pipeline system more cache address comparator involvement is needed to coordinate an access.
One type of high speed, multi-level cache hierarchical system having a multi-stage pipeline is based on the high performance model 680X0 line of CISC microprocessors by Motorola Incorporated, Schaumburg, Ill. This line of microprocessors includes the 68020 and the 68030. Since the 68020 and the 68030 have three stage pipelines for their buses, they also have comprehensive bus controlling features. Each 68020 or 68030 microprocessor has a bus error (BERR) input which informs the microprocessor that a bus error of some type has occurred and, under some conditions, helps determine if the current bus instruction should be rerun or aborted. Each 680X0 microprocessor also has a halt (HALT) input which unconditionally halts the activity to and from the external system bus and thus holds the pipeline in a fixed state when this input is activated. Unfortunately, a cache address comparator fashioned after the TMS-2150, but which uses the bus error rerun and the halt functions of the 680X0 microprocessors, is not available.
The 68020 microprocessor has a small, internal instruction cache. The 68030 microprocessor has a small, internal instruction cache, and a small, internal data cache. These internal caches can be filled quickly by using a burst fill mode to transfer data between memory and the microprocessor. A burst fill is initiated by the microprocessor when a cache burst request (CBREQ) output along with the first address of the cache burst are activated. The specified response to a cache burst request is a cache burst acknowledge (CBACK) and four long words of data starting at the first address of the cache burst and continuing with the three incrementally higher addresses. If available in an external cache, these four long words of thirty-two bits should be transferred to the microprocessor in a burst fill within the five system clock cycles. Unfortunately, a cache address comparator, fashioned after the TMS 2150, which has the logic circuitry necessary to control the response of an external cache to a burst fill request, does not exist.
It is an object of this invention to provide a cache address comparator integrated circuit that has bus error and bus halt outputs for controlling a multi-staged pipelined microprocessor.
It is another object of this invention to provide the a cache address comparator integrated circuit which has bus error and halt outputs for the control of a burst fill operation to itself after a cache miss.